1. Repositório Aberto da Universidade do Porto
  2. FEUP - Faculdade de Engenharia
  3. FEUP - Artigo em Livro de Atas de Conferência Internacional
Please use this identifier to cite or link to this item: https://hdl.handle.net/10216/84553
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dc.creatorGustavo R. Alves
dc.creatorManuel G. Gericota
dc.creatorJosé L. Ramalho
dc.creatorJosé M. M. Ferreira
dc.date.accessioned2019-02-02T04:16:27Z-
dc.date.available2019-02-02T04:16:27Z-
dc.date.issued1993
dc.identifier.othersigarra:52337
dc.identifier.urihttps://repositorio-aberto.up.pt/handle/10216/84553-
dc.description.abstractBoundary scan is now the most promising technology for testing high-complexity printed circuit boards. The number of BST components available to board-level designers is however still restricted, limiting the achievable fault coverage. The requirements to improve board-level testability are analyzed, and a corresponding set of testability building blocks are proposed. A high flexibility and reduced cost solution is described, which implements these blocks on medium-complexity PLDs using a simple and powerful HDL.
dc.language.isoeng
dc.relation.ispartofProceedings of the European Design Automation Conference
dc.rightsopenAccess
dc.rights.urihttps://creativecommons.org/licenses/by-nc/4.0/
dc.subjectEngenharia electrotécnica, Engenharia electrotécnica, electrónica e informática
dc.subjectElectrical engineering, Electrical engineering, Electronic engineering, Information engineering
dc.titleHDL approach to board-level BIST
dc.typeArtigo em Livro de Atas de Conferência Internacional
dc.contributor.uportoFaculdade de Engenharia
dc.identifier.doi10.1109/EURDAC.1993.410669
dc.subject.fosCiências da engenharia e tecnologias::Engenharia electrotécnica, electrónica e informática
dc.subject.fosEngineering and technology::Electrical engineering, Electronic engineering, Information engineering
Appears in Collections:FEUP - Artigo em Livro de Atas de Conferência Internacional

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