Please use this identifier to cite or link to this item:
https://hdl.handle.net/10216/84523| Author(s): | José Martins Ferreira José Silva Matos F. Jong |
| Title: | Board testing with boundary scan: TPG strategy |
| Issue Date: | 1990 |
| Subject: | Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática Electrical engineering, Electrical engineering, Electronic engineering, Information engineering |
| Scientific areas: | Ciências da engenharia e tecnologias::Engenharia electrotécnica, electrónica e informática Engineering and technology::Electrical engineering, Electronic engineering, Information engineering |
| URI: | https://repositorio-aberto.up.pt/handle/10216/84523 |
| Source: | 7th European Design for Testability Workshop |
| Document Type: | Artigo em Livro de Atas de Conferência Internacional |
| Rights: | openAccess |
| License: | https://creativecommons.org/licenses/by-nc/4.0/ |
| Appears in Collections: | FEUP - Artigo em Livro de Atas de Conferência Internacional |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| 52595.pdf | Board Testing with Boundary Scan: TPG Strategy | 646.15 kB | Adobe PDF |  View/Open |
This item is licensed under a Creative Commons License
