Please use this identifier to cite or link to this item: http://hdl.handle.net/10216/84523
Author(s): José Martins Ferreira
José Silva Matos
F. Jong
Title: Board testing with boundary scan: TPG strategy
Issue Date: 1990
Subject: Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática
Electrical engineering, Electrical engineering, Electronic engineering, Information engineering
Call Number: 52595
URI: http://hdl.handle.net/10216/84523
Source: 7th European Design for Testability Workshop
Document Type: Artigo em Livro de Atas de Conferência Internacional
Rights: openAccess
License: https://creativecommons.org/licenses/by-nc/4.0/
Appears in Collections:FEUP - Artigo em Livro de Atas de Conferência Internacional

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