Please use this identifier to cite or link to this item: http://hdl.handle.net/10216/96200
Author(s): Carlos Morra
João Cardoso
João Bispo
Juergen Becker
Title: Retargeting, evaluating, and generating reconfigurable array-based architectures
Issue Date: 2008
Abstract: Coarse-grained reconfigurable architectures have proven their value as programmable accelerators for general purpose processors. For early evaluation of those architectures, we need an approach able to exploit and retarget different Processing Elements (PEs) while maintaining the same compilation flow. Bearing in mind those aspects, this paper describes an approach able to map, evaluate and generate reconfigurable architectures based on an array of PEs. We use Rewriting Logic to map computations described by imperative programming languages to the PEs of the target architecture, a VHDL generation step to prototype the architectures being evaluated, and a clock cycle-based simulator to achieve first assessments about the performance of those architectures. In order to show the potential of our approach, we present results of 1-D coarse-grained reconfigurable arrays as accelerator softcores implemented in an FPGA, and the effects of different PE's structures and complexities.
Subject: Engenharia de computadores, Engenharia electrotécnica, electrónica e informática
Computer engineering, Electrical engineering, Electronic engineering, Information engineering
Call Number: 67908
URI: http://hdl.handle.net/10216/96200
Source: 2008 SYMPOSIUM ON APPLICATION SPECIFIC PROCESSORS
Document Type: Artigo em Livro de Atas de Conferência Internacional
Rights: restrictedAccess
Appears in Collections:FEUP - Artigo em Livro de Atas de Conferência Internacional

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