1. Repositório Aberto da Universidade do Porto
  2. FEUP - Faculdade de Engenharia
  3. FEUP - Artigo em Livro de Atas de Conferência Internacional
Please use this identifier to cite or link to this item: https://hdl.handle.net/10216/85051
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dc.creatorGustavo R. Alves
dc.creatorTelmo Pedro Gomes Amaral
dc.creatorJosé M. Martins Ferreira
dc.date.accessioned2022-09-15T14:33:11Z-
dc.date.available2022-09-15T14:33:11Z-
dc.date.issued1999
dc.identifier.othersigarra:65721
dc.identifier.urihttps://hdl.handle.net/10216/85051-
dc.description.abstractA good verification strategy should bring near the simulation and real functioning environments. In this paper we describe a system-level co-verification strategy that uses a common flow for functional simulation, timing simulation and functional debug. This last step requires the use of a BST infrastructure, now widely available on commercial devices, specially on programmable devices with medium / large pin-counts.
dc.language.isoeng
dc.relation.ispartofProceedings of the Design Automation and Test in Europe Conference - DATE'99
dc.rightsopenAccess
dc.rights.urihttps://creativecommons.org/licenses/by-nc/4.0/
dc.subjectEngenharia electrotécnica, Engenharia electrotécnica, electrónica e informática
dc.subjectElectrical engineering, Electrical engineering, Electronic engineering, Information engineering
dc.titleA Framework for System-Level Co-Verification Using the BST Infrastructure
dc.typeArtigo em Livro de Atas de Conferência Internacional
dc.contributor.uportoFaculdade de Engenharia
dc.subject.fosCiências da engenharia e tecnologias::Engenharia electrotécnica, electrónica e informática
dc.subject.fosEngineering and technology::Electrical engineering, Electronic engineering, Information engineering
Appears in Collections:FEUP - Artigo em Livro de Atas de Conferência Internacional

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