Please use this identifier to cite or link to this item: http://hdl.handle.net/10216/85045
Author(s): Manuel Gericota
Gustavo Costa Alves
Miguel L. Silva
José Martins Ferreira
Title: DRAFT: An On-line Fault Detection Method for Dynamic and Partially Reconfigurable FPGAs
Issue Date: 2001
Abstract: Reconfigurable systems have benefited of the novel partial dynamic reconfiguration features of recent FPGA devices. Enabling the concurrent reconfiguration without disturbing system operation, this technology has raised a new test challenge: to assure a continuously fault-free operation, independently of the circuit present after many reconfiguration processes, testing the FPGA without disturbing the whole system operation. Re-using the IEEE 1149.1 infrastructure, already widely used for In-System Programming, and exploiting the same dynamic and partially reconfigurable features underlying this test challenge, this paper develops a new structural concurrent test approach able to detect faults and introduce fault tolerance features, without disturbing system operation, in the field and throughout its lifetime.
Subject: Engenharia electrotécnica, Ciências da educação
Electrical engineering, Educational sciences
Call Number: 53087
URI: http://hdl.handle.net/10216/85045
Source: Proceedings of the 7th Internatinal On-Line Testing Workshop IOLTW'01
Document Type: Artigo em Livro de Atas de Conferência Internacional
Rights: openAccess
License: https://creativecommons.org/licenses/by-nc/4.0/
Appears in Collections:FEUP - Artigo em Livro de Atas de Conferência Internacional

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