Please use this identifier to cite or link to this item:
https://hdl.handle.net/10216/85022| Author(s): | Manuel G. Gericota Gustavo R. Alves Miguel L. Silva José M. Ferreira |
| Title: | DRAFT: A scanning test methodology for dynamic and partially reconfigurable FPGAs |
| Issue Date: | 2001 |
| Abstract: | A new class of FPGAs that enable partial and dynamic reconfiguration without disturbing system operation, raised a new test challenge: how to assure a continuously fault-free operation, independently of the circuit present after many reconfiguration processes. A new on-line test method for those FPGAs is proposed, based on a scanning methodology and in the reuse of the IEEE 1149.1 Boundary Scan test infrastructure, already widely employed for In-System Programming. |
| Subject: | Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática Electrical engineering, Electrical engineering, Electronic engineering, Information engineering |
| Scientific areas: | Ciências da engenharia e tecnologias::Engenharia electrotécnica, electrónica e informática Engineering and technology::Electrical engineering, Electronic engineering, Information engineering |
| URI: | https://hdl.handle.net/10216/85022 |
| Source: | Proceedings of the European Test Workshop ETW'01 |
| Document Type: | Artigo em Livro de Atas de Conferência Internacional |
| Rights: | openAccess |
| License: | https://creativecommons.org/licenses/by-nc/4.0/ |
| Appears in Collections: | FEUP - Artigo em Livro de Atas de Conferência Internacional |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| 65724.pdf | DRAFT: A Scanning Test Methodology for Dynamic and Partially Reconfigurable FPGAs | 157.8 kB | Adobe PDF |  View/Open |
This item is licensed under a Creative Commons License
