1. Repositório Aberto da Universidade do Porto
  2. FEUP - Faculdade de Engenharia
  3. FEUP - Artigo em Livro de Atas de Conferência Internacional
Please use this identifier to cite or link to this item: https://hdl.handle.net/10216/85022
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dc.creatorManuel G. Gericota
dc.creatorGustavo R. Alves
dc.creatorMiguel L. Silva
dc.creatorJosé M. Ferreira
dc.date.accessioned2022-09-13T07:50:44Z-
dc.date.available2022-09-13T07:50:44Z-
dc.date.issued2001
dc.identifier.othersigarra:65724
dc.identifier.urihttps://hdl.handle.net/10216/85022-
dc.description.abstractA new class of FPGAs that enable partial and dynamic reconfiguration without disturbing system operation, raised a new test challenge: how to assure a continuously fault-free operation, independently of the circuit present after many reconfiguration processes. A new on-line test method for those FPGAs is proposed, based on a scanning methodology and in the reuse of the IEEE 1149.1 Boundary Scan test infrastructure, already widely employed for In-System Programming.
dc.language.isoeng
dc.relation.ispartofProceedings of the European Test Workshop ETW'01
dc.rightsopenAccess
dc.rights.urihttps://creativecommons.org/licenses/by-nc/4.0/
dc.subjectEngenharia electrotécnica, Engenharia electrotécnica, electrónica e informática
dc.subjectElectrical engineering, Electrical engineering, Electronic engineering, Information engineering
dc.titleDRAFT: A scanning test methodology for dynamic and partially reconfigurable FPGAs
dc.typeArtigo em Livro de Atas de Conferência Internacional
dc.contributor.uportoFaculdade de Engenharia
dc.subject.fosCiências da engenharia e tecnologias::Engenharia electrotécnica, electrónica e informática
dc.subject.fosEngineering and technology::Electrical engineering, Electronic engineering, Information engineering
Appears in Collections:FEUP - Artigo em Livro de Atas de Conferência Internacional

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