DRAFT: A scanning test methodology for dynamic and partially reconfigurable FPGAs

Manuel G. Gericota; Gustavo R. Alves; Miguel L. Silva; José M. Ferreira

Utilize este identificador para referenciar este registo: https://hdl.handle.net/10216/85022

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Campo DC	Valor	Idioma
dc.creator	Manuel G. Gericota
dc.creator	Gustavo R. Alves
dc.creator	Miguel L. Silva
dc.creator	José M. Ferreira
dc.date.accessioned	2022-09-13T07:50:44Z	-
dc.date.available	2022-09-13T07:50:44Z	-
dc.date.issued	2001
dc.identifier.other	sigarra:65724
dc.identifier.uri	https://hdl.handle.net/10216/85022	-
dc.description.abstract	A new class of FPGAs that enable partial and dynamic reconfiguration without disturbing system operation, raised a new test challenge: how to assure a continuously fault-free operation, independently of the circuit present after many reconfiguration processes. A new on-line test method for those FPGAs is proposed, based on a scanning methodology and in the reuse of the IEEE 1149.1 Boundary Scan test infrastructure, already widely employed for In-System Programming.
dc.language.iso	eng
dc.relation.ispartof	Proceedings of the European Test Workshop ETW'01
dc.rights	openAccess
dc.rights.uri	https://creativecommons.org/licenses/by-nc/4.0/
dc.subject	Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática
dc.subject	Electrical engineering, Electrical engineering, Electronic engineering, Information engineering
dc.title	DRAFT: A scanning test methodology for dynamic and partially reconfigurable FPGAs
dc.type	Artigo em Livro de Atas de Conferência Internacional
dc.contributor.uporto	Faculdade de Engenharia
dc.subject.fos	Ciências da engenharia e tecnologias::Engenharia electrotécnica, electrónica e informática
dc.subject.fos	Engineering and technology::Electrical engineering, Electronic engineering, Information engineering
Aparece nas coleções:	FEUP - Artigo em Livro de Atas de Conferência Internacional

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