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Author(s): Gustavo Costa Alves
Marcelo Lubaszewski
Margrit Krug
José Martins Ferreira
Title: From circuit simulation to circuit verification: an internal+boundary-scan-based solution
Issue Date: 2000
Abstract: Matching the results obtained from circuit simulation with those extracted from circuit functioning is a common stage of the final verification process. Many current verification techniques use the I/O vectors produced during functional and / or timing simulation, for creating the test vectors to be applied / compared against the circuit responses. Techniques that are more complete include extracting the values of internal sequential nodes and comparing these using internal scans. This paper describes such a solution for verifying digital designs implemented in currently commercial available CPLDs. The test program encompasses the design and development phase, namely: the file containing the results from simulation, the BSDL file, an internal scan chain description file, and one file containing the user options.
Subject: Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática
Electrical engineering, Electrical engineering, Electronic engineering, Information engineering
Scientific areas: Ciências da engenharia e tecnologias::Engenharia electrotécnica, electrónica e informática
Engineering and technology::Electrical engineering, Electronic engineering, Information engineering
Source: Proceedings of the European Test Workshop ETW'00
Document Type: Artigo em Livro de Atas de Conferência Internacional
Rights: openAccess
Appears in Collections:FEUP - Artigo em Livro de Atas de Conferência Internacional

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