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https://hdl.handle.net/10216/85012
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DC Field | Value | Language |
---|---|---|
dc.creator | Gustavo Costa Alves | |
dc.creator | Marcelo Lubaszewski | |
dc.creator | Margrit Krug | |
dc.creator | José Martins Ferreira | |
dc.date.accessioned | 2022-09-08T23:52:35Z | - |
dc.date.available | 2022-09-08T23:52:35Z | - |
dc.date.issued | 2000 | |
dc.identifier.other | sigarra:53307 | |
dc.identifier.uri | https://hdl.handle.net/10216/85012 | - |
dc.description.abstract | Matching the results obtained from circuit simulation with those extracted from circuit functioning is a common stage of the final verification process. Many current verification techniques use the I/O vectors produced during functional and / or timing simulation, for creating the test vectors to be applied / compared against the circuit responses. Techniques that are more complete include extracting the values of internal sequential nodes and comparing these using internal scans. This paper describes such a solution for verifying digital designs implemented in currently commercial available CPLDs. The test program encompasses the design and development phase, namely: the file containing the results from simulation, the BSDL file, an internal scan chain description file, and one file containing the user options. | |
dc.language.iso | eng | |
dc.relation.ispartof | Proceedings of the European Test Workshop ETW'00 | |
dc.rights | openAccess | |
dc.rights.uri | https://creativecommons.org/licenses/by-nc/4.0/ | |
dc.subject | Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática | |
dc.subject | Electrical engineering, Electrical engineering, Electronic engineering, Information engineering | |
dc.title | From circuit simulation to circuit verification: an internal+boundary-scan-based solution | |
dc.type | Artigo em Livro de Atas de Conferência Internacional | |
dc.contributor.uporto | Faculdade de Engenharia | |
dc.subject.fos | Ciências da engenharia e tecnologias::Engenharia electrotécnica, electrónica e informática | |
dc.subject.fos | Engineering and technology::Electrical engineering, Electronic engineering, Information engineering | |
Appears in Collections: | FEUP - Artigo em Livro de Atas de Conferência Internacional |
Files in This Item:
File | Description | Size | Format | |
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53307.pdf | From Circuit Simulation to Circuit Verification: An Internal + Boundary- Scan-Based Solution | 270.12 kB | Adobe PDF | View/Open |
This item is licensed under a Creative Commons License