Utilize este identificador para referenciar este registo: https://hdl.handle.net/10216/85005
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Campo DCValorIdioma
dc.creatorManuel G. Gericota
dc.creatorGustavo R. Alves
dc.creatorMiguel L. Silva
dc.creatorJosé M. Ferreira
dc.date.accessioned2022-09-09T08:28:08Z-
dc.date.available2022-09-09T08:28:08Z-
dc.date.issued2002
dc.identifier.othersigarra:66138
dc.identifier.urihttps://hdl.handle.net/10216/85005-
dc.description.abstractThis poster presents the first truly non-intrusive structural concurrent test approach, with the objective of testing partially and dynamically reconfigurable SRAM-based FPGAs without disturbing their operation. This is accomplished by using a new methodology to carry out the replication of active Configurable Logic Blocks (CLBs), i.e. CLBs that are part of an implemented function that is actually being used by the system, releasing it to be tested in a way that is completely transparent to the system.
dc.language.isoeng
dc.relation.ispartofProceedings of the Design, Automation and Test in Europe Conference (DATE'02)
dc.rightsopenAccess
dc.rights.urihttps://creativecommons.org/licenses/by-nc/4.0/
dc.subjectEngenharia electrotécnica, Engenharia electrotécnica, electrónica e informática
dc.subjectElectrical engineering, Electrical engineering, Electronic engineering, Information engineering
dc.titleA novel methodology for the concurrent test of partial and dynamically reconfigurable SRAM-based FPGAs
dc.typeArtigo em Livro de Atas de Conferência Internacional
dc.contributor.uportoFaculdade de Engenharia
dc.identifier.doi10.1109/DATE.2002.998482
dc.subject.fosCiências da engenharia e tecnologias::Engenharia electrotécnica, electrónica e informática
dc.subject.fosEngineering and technology::Electrical engineering, Electronic engineering, Information engineering
Aparece nas coleções:FEUP - Artigo em Livro de Atas de Conferência Internacional

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