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Author(s): Gustavo R. Alves
Marcelo S. Lubaszewski
Margrit Reni Krug
José M. Martins Ferreira
Title: An automated verification process based on scan techniques
Issue Date: 2000
Abstract: Matching the results achieved during circuit simulation with those extracted from circuit operation is a common verification process. A large number of current verification techniques use the input / output vectors produced during functional simulation as the test vectors applied / compared against the circuit responses. Techniques that are more complete include extracting the values of internal sequential nodes and comparing these using internal scans. This paper describes a solution for verifying digital designs implemented in commercially available CLPDs. All internal flip-flops are included in a scan chain accessible through the BST infrastructure (through a user-defined optional instruction), while the BS cells are used to apply the input test vectors and capture the circuit responses. These BS cells can either belong to the device-under-test or to other devices, in the former case through the optional INTEST instruction and in the latter through the mandatory EXTEST instruction. To speed up the verification process, the test program is automatically generated from information that encompasses the design and development phase.
Subject: Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática
Electrical engineering, Electrical engineering, Electronic engineering, Information engineering
Scientific areas: Ciências da engenharia e tecnologias::Engenharia electrotécnica, electrónica e informática
Engineering and technology::Electrical engineering, Electronic engineering, Information engineering
Source: Proceedings of 7th Biennial Baltic Electronics Conference BEC'00
Document Type: Artigo em Livro de Atas de Conferência Internacional
Rights: openAccess
Appears in Collections:FEUP - Artigo em Livro de Atas de Conferência Internacional

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