Please use this identifier to cite or link to this item: https://hdl.handle.net/10216/84994
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dc.creatorGustavo R. Alves
dc.creatorMarcelo S. Lubaszewski
dc.creatorMargrit Reni Krug
dc.creatorJosé M. Martins Ferreira
dc.date.accessioned2019-02-05T02:19:21Z-
dc.date.available2019-02-05T02:19:21Z-
dc.date.issued2000
dc.identifier.othersigarra:53933
dc.identifier.urihttps://repositorio-aberto.up.pt/handle/10216/84994-
dc.description.abstractMatching the results achieved during circuit simulation with those extracted from circuit operation is a common verification process. A large number of current verification techniques use the input / output vectors produced during functional simulation as the test vectors applied / compared against the circuit responses. Techniques that are more complete include extracting the values of internal sequential nodes and comparing these using internal scans. This paper describes a solution for verifying digital designs implemented in commercially available CLPDs. All internal flip-flops are included in a scan chain accessible through the BST infrastructure (through a user-defined optional instruction), while the BS cells are used to apply the input test vectors and capture the circuit responses. These BS cells can either belong to the device-under-test or to other devices, in the former case through the optional INTEST instruction and in the latter through the mandatory EXTEST instruction. To speed up the verification process, the test program is automatically generated from information that encompasses the design and development phase.
dc.language.isoeng
dc.relation.ispartofProceedings of 7th Biennial Baltic Electronics Conference BEC'00
dc.rightsopenAccess
dc.rights.urihttps://creativecommons.org/licenses/by-nc/4.0/
dc.subjectEngenharia electrotécnica, Engenharia electrotécnica, electrónica e informática
dc.subjectElectrical engineering, Electrical engineering, Electronic engineering, Information engineering
dc.titleAn automated verification process based on scan techniques
dc.typeArtigo em Livro de Atas de Conferência Internacional
dc.contributor.uportoFaculdade de Engenharia
dc.subject.fosCiências da engenharia e tecnologias::Engenharia electrotécnica, electrónica e informática
dc.subject.fosEngineering and technology::Electrical engineering, Electronic engineering, Information engineering
Appears in Collections:FEUP - Artigo em Livro de Atas de Conferência Internacional

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