A modular architecture for BIST of boundary scan boards

José M. M. Ferreira; Filipe S. Pinto; José S. Matos

doi:10.1109/EUASIC.1992.228027

Utilize este identificador para referenciar este registo: https://hdl.handle.net/10216/84586

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Campo DC	Valor	Idioma
dc.creator	José M. M. Ferreira
dc.creator	Filipe S. Pinto
dc.creator	José S. Matos
dc.date.accessioned	2019-02-01T04:17:33Z	-
dc.date.available	2019-02-01T04:17:33Z	-
dc.date.issued	1992
dc.identifier.other	sigarra:52333
dc.identifier.uri	https://repositorio-aberto.up.pt/handle/10216/84586	-
dc.description.abstract	A board-level BIST architecture for boards loaded with ASICs and VLSI components, compliant with the IEEE 1149.1 BST standard, is described. This BIST architecture consists of a test processor core, with an optimized architecture for controlling the board-level BST (boundary scan test) infrastructure, an optional system-level testability bus interface, to be included when a system-level test strategy is to be implemented, and a ROM containing the test program, which is automatically generated by an ATPG tool.
dc.language.iso	eng
dc.relation.ispartof	Proceedings of the EUROASIC Conference
dc.rights	openAccess
dc.rights.uri	https://creativecommons.org/licenses/by-nc/4.0/
dc.subject	Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática
dc.subject	Electrical engineering, Electrical engineering, Electronic engineering, Information engineering
dc.title	A modular architecture for BIST of boundary scan boards
dc.type	Artigo em Livro de Atas de Conferência Internacional
dc.contributor.uporto	Faculdade de Engenharia
dc.identifier.doi	10.1109/EUASIC.1992.228027
dc.subject.fos	Ciências da engenharia e tecnologias::Engenharia electrotécnica, electrónica e informática
dc.subject.fos	Engineering and technology::Electrical engineering, Electronic engineering, Information engineering
Aparece nas coleções:	FEUP - Artigo em Livro de Atas de Conferência Internacional

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