Please use this identifier to cite or link to this item:
https://hdl.handle.net/10216/84586| Author(s): | José M. M. Ferreira Filipe S. Pinto José S. Matos |
| Title: | A modular architecture for BIST of boundary scan boards |
| Issue Date: | 1992 |
| Abstract: | A board-level BIST architecture for boards loaded with ASICs and VLSI components, compliant with the IEEE 1149.1 BST standard, is described. This BIST architecture consists of a test processor core, with an optimized architecture for controlling the board-level BST (boundary scan test) infrastructure, an optional system-level testability bus interface, to be included when a system-level test strategy is to be implemented, and a ROM containing the test program, which is automatically generated by an ATPG tool. |
| Subject: | Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática Electrical engineering, Electrical engineering, Electronic engineering, Information engineering |
| Scientific areas: | Ciências da engenharia e tecnologias::Engenharia electrotécnica, electrónica e informática Engineering and technology::Electrical engineering, Electronic engineering, Information engineering |
| URI: | https://repositorio-aberto.up.pt/handle/10216/84586 |
| Source: | Proceedings of the EUROASIC Conference |
| Document Type: | Artigo em Livro de Atas de Conferência Internacional |
| Rights: | openAccess |
| License: | https://creativecommons.org/licenses/by-nc/4.0/ |
| Appears in Collections: | FEUP - Artigo em Livro de Atas de Conferência Internacional |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| 52333.pdf | A Modular Architecture for BIST of Boundary Scan Boards | 292.81 kB | Adobe PDF |  View/Open |
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