Please use this identifier to cite or link to this item:
https://hdl.handle.net/10216/84575| Author(s): | José M. M. Ferreira Filipe S. Pinto José S. Matos |
| Title: | Automatic generation of a single-chip solution for board-level BIST of boundary scan boards |
| Issue Date: | 1992 |
| Abstract: | The automatic generation of a hierarchical self-test architecture for boards with boundary scan test (BST) is described, based on a test processor specifically designed to implement the basic operations required to control the BST infrastructure. An ATPG module generates the ROM containing the test program, allowing a single-chip self-test solution with minimal design-for-testability overhead. The same test processor may be used without internal ROM, when a single-chip solution is not desirable. |
| Subject: | Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática Electrical engineering, Electrical engineering, Electronic engineering, Information engineering |
| Scientific areas: | Ciências da engenharia e tecnologias::Engenharia electrotécnica, electrónica e informática Engineering and technology::Electrical engineering, Electronic engineering, Information engineering |
| DOI: | 10.1109/EDAC.1992.205913 |
| URI: | https://repositorio-aberto.up.pt/handle/10216/84575 |
| Source: | Proceedings of the European Design Automation Conference |
| Document Type: | Artigo em Livro de Atas de Conferência Internacional |
| Rights: | openAccess |
| License: | https://creativecommons.org/licenses/by-nc/4.0/ |
| Appears in Collections: | FEUP - Artigo em Livro de Atas de Conferência Internacional |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| 65797.pdf | Automatic Generation of a Single-Chip Solution for BIST of Boundary Scan Boards | 355.83 kB | Adobe PDF |  View/Open |
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