Please use this identifier to cite or link to this item:
Author(s): José M. M. Ferreira
Filipe S. Pinto
José S. Matos
Title: Automatic generation of a single-chip solution for board-level BIST of boundary scan boards
Issue Date: 1992
Abstract: The automatic generation of a hierarchical self-test architecture for boards with boundary scan test (BST) is described, based on a test processor specifically designed to implement the basic operations required to control the BST infrastructure. An ATPG module generates the ROM containing the test program, allowing a single-chip self-test solution with minimal design-for-testability overhead. The same test processor may be used without internal ROM, when a single-chip solution is not desirable.
Subject: Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática
Electrical engineering, Electrical engineering, Electronic engineering, Information engineering
Scientific areas: Ciências da engenharia e tecnologias::Engenharia electrotécnica, electrónica e informática
Engineering and technology::Electrical engineering, Electronic engineering, Information engineering
Source: Proceedings of the European Design Automation Conference
Document Type: Artigo em Livro de Atas de Conferência Internacional
Rights: openAccess
Appears in Collections:FEUP - Artigo em Livro de Atas de Conferência Internacional

Files in This Item:
File Description SizeFormat 
65797.pdfAutomatic Generation of a Single-Chip Solution for BIST of Boundary Scan Boards355.83 kBAdobe PDFThumbnail

This item is licensed under a Creative Commons License Creative Commons