Utilize este identificador para referenciar este registo:
https://hdl.handle.net/10216/84573Registo completo
| Campo DC | Valor | Idioma |
|---|---|---|
| dc.creator | José S. Matos | |
| dc.creator | Filipe S. Pinto | |
| dc.creator | José M. M. Ferreira | |
| dc.date.accessioned | 2022-09-11T15:51:11Z | - |
| dc.date.available | 2022-09-11T15:51:11Z | - |
| dc.date.issued | 1992 | |
| dc.identifier.other | sigarra:53148 | |
| dc.identifier.uri | https://hdl.handle.net/10216/84573 | - |
| dc.description.abstract | A test controller for BIST of Boundary Scan Boards is described. It consists of a test processor core, with an optimized architecture for controlling the board-level BST infrastructure, and a system level testability bus interjace, allowing the implementation of a hierarchical test strategy. Automatic test pattern generation for this dedicated processor simplifies the task of providing a board-level BIST solution. | |
| dc.language.iso | eng | |
| dc.relation.ispartof | Proceedings of the IEEE International Test Conference | |
| dc.rights | openAccess | |
| dc.rights.uri | https://creativecommons.org/licenses/by-nc/4.0/ | |
| dc.subject | Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática | |
| dc.subject | Electrical engineering, Electrical engineering, Electronic engineering, Information engineering | |
| dc.title | A boundary scan test controller for hierarchical BIST | |
| dc.type | Artigo em Livro de Atas de Conferência Internacional | |
| dc.contributor.uporto | Faculdade de Engenharia | |
| dc.identifier.doi | 10.1109/TEST.1992.527822 | |
| dc.subject.fos | Ciências da engenharia e tecnologias::Engenharia electrotécnica, electrónica e informática | |
| dc.subject.fos | Engineering and technology::Electrical engineering, Electronic engineering, Information engineering | |
| Aparece nas coleções: | FEUP - Artigo em Livro de Atas de Conferência Internacional | |
Ficheiros deste registo:
| Ficheiro | Descrição | Tamanho | Formato | |
|---|---|---|---|---|
| 53148.pdf | A Boundary Scan Test Controller for Hierarchical BIST | 384.62 kB | Adobe PDF |  Ver/Abrir |
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