1. Repositório Aberto da Universidade do Porto
  2. FEUP - Faculdade de Engenharia
  3. FEUP - Artigo em Livro de Atas de Conferência Internacional
Please use this identifier to cite or link to this item: https://hdl.handle.net/10216/84573
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dc.creatorJosé S. Matos
dc.creatorFilipe S. Pinto
dc.creatorJosé M. M. Ferreira
dc.date.accessioned2022-09-11T15:51:11Z-
dc.date.available2022-09-11T15:51:11Z-
dc.date.issued1992
dc.identifier.othersigarra:53148
dc.identifier.urihttps://hdl.handle.net/10216/84573-
dc.description.abstractA test controller for BIST of Boundary Scan Boards is described. It consists of a test processor core, with an optimized architecture for controlling the board-level BST infrastructure, and a system level testability bus interjace, allowing the implementation of a hierarchical test strategy. Automatic test pattern generation for this dedicated processor simplifies the task of providing a board-level BIST solution.
dc.language.isoeng
dc.relation.ispartofProceedings of the IEEE International Test Conference
dc.rightsopenAccess
dc.rights.urihttps://creativecommons.org/licenses/by-nc/4.0/
dc.subjectEngenharia electrotécnica, Engenharia electrotécnica, electrónica e informática
dc.subjectElectrical engineering, Electrical engineering, Electronic engineering, Information engineering
dc.titleA boundary scan test controller for hierarchical BIST
dc.typeArtigo em Livro de Atas de Conferência Internacional
dc.contributor.uportoFaculdade de Engenharia
dc.identifier.doi10.1109/TEST.1992.527822
dc.subject.fosCiências da engenharia e tecnologias::Engenharia electrotécnica, electrónica e informática
dc.subject.fosEngineering and technology::Electrical engineering, Electronic engineering, Information engineering
Appears in Collections:FEUP - Artigo em Livro de Atas de Conferência Internacional

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