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https://hdl.handle.net/10216/89313
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DC Field | Value | Language |
---|---|---|
dc.creator | Carlos Jorge Matos Carneiro de Sousa | |
dc.date.accessioned | 2019-02-02T09:59:55Z | - |
dc.date.available | 2019-02-02T09:59:55Z | - |
dc.date.issued | 2016-07-21 | |
dc.date.submitted | 2016-07-27 | |
dc.identifier.other | sigarra:170143 | |
dc.identifier.uri | https://repositorio-aberto.up.pt/handle/10216/89313 | - |
dc.description | Nowadays, the volume of data and application complexity is growing sharply. Simultaneously, embedded systems are becoming more widely used. To keep up with the increasing need of computational power, it is required to design faster and more power efficient circuits. However, as size decreases and the density of circuits increases the present day solutions are steadily hitting their maximum capability. With this in mind, it is necessary to develop new computer architectures. One approach is to have a dynamically reconfigurable system. The existence of configurable hardware would allow optimizing the execution of small parts of the application's execution, leading to an overall speedup of the system. The main goal of this project is to implement an embedded scheduler capable of, during runtime, generating the specification and the operation schedule of a Reconfigurable Processing Unit that accelerates execution of application hot spots identified from binary execution traces. | |
dc.language.iso | por | |
dc.rights | openAccess | |
dc.subject | Engenharia electrotécnica, electrónica e informática | |
dc.subject | Electrical engineering, Electronic engineering, Information engineering | |
dc.title | Embedded Scheduler for Dynamically Reconfigurable Accelerators | |
dc.type | Dissertação | |
dc.contributor.uporto | Faculdade de Engenharia | |
dc.identifier.tid | 201298961 | |
dc.subject.fos | Ciências da engenharia e tecnologias::Engenharia electrotécnica, electrónica e informática | |
dc.subject.fos | Engineering and technology::Electrical engineering, Electronic engineering, Information engineering | |
thesis.degree.discipline | Mestrado Integrado em Engenharia Electrotécnica e de Computadores | |
thesis.degree.grantor | Faculdade de Engenharia | |
thesis.degree.grantor | Universidade do Porto | |
thesis.degree.level | 1 | |
Appears in Collections: | FEUP - Dissertação |
Files in This Item:
File | Description | Size | Format | |
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170143.pdf | Embedded Scheduler for Dynamically Reconfigurable Accelerators | 822.22 kB | Adobe PDF | View/Open |
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