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Author(s): Carlos Jorge Matos Carneiro de Sousa
Title: Embedded Scheduler for Dynamically Reconfigurable Accelerators
Issue Date: 2016-07-21
Description: Nowadays, the volume of data and application complexity is growing sharply. Simultaneously, embedded systems are becoming more widely used. To keep up with the increasing need of computational power, it is required to design faster and more power efficient circuits. However, as size decreases and the density of circuits increases the present day solutions are steadily hitting their maximum capability. With this in mind, it is necessary to develop new computer architectures. One approach is to have a dynamically reconfigurable system. The existence of configurable hardware would allow optimizing the execution of small parts of the application's execution, leading to an overall speedup of the system. The main goal of this project is to implement an embedded scheduler capable of, during runtime, generating the specification and the operation schedule of a Reconfigurable Processing Unit that accelerates execution of application hot spots identified from binary execution traces.
Subject: Engenharia electrotécnica, electrónica e informática
Electrical engineering, Electronic engineering, Information engineering
TID identifier : 201298961
Document Type: Dissertação
Rights: openAccess
Appears in Collections:FEUP - Dissertação

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