Please use this identifier to cite or link to this item: https://hdl.handle.net/10216/85053
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dc.creatorManuel Gericota
dc.creatorGustavo Costa Alves
dc.creatorMiguel L. Silva
dc.creatorJosé Martins Ferreira
dc.date.accessioned2022-09-06T19:34:36Z-
dc.date.available2022-09-06T19:34:36Z-
dc.date.issued2001
dc.identifier.othersigarra:69352
dc.identifier.urihttps://hdl.handle.net/10216/85053-
dc.description.abstractThe use of partial and dynamically reconfigurable FPGAs in reconfigurable systems opens exciting possibilities, since they enable the concurrent reconfiguration of part of the system without interrupting its operation. Nevertheless, larger dies and the use of smaller submicron scales in the manufacturing of this new kind of FPGAs increase the probability of failures after many reconfiguration processes. New methods of test and fault tolerance are therefore required, capable of ensuring system reliability. This paper presents improvements to our RaT Freed Resources technique, a structural concurrent test approach able to detect and diagnose faults without disturbing system operation, throughout its lifetime.
dc.language.isoeng
dc.relation.ispartofProceedings of the Design of Circuits and Integrated Systems conference DCIS-01
dc.rightsopenAccess
dc.rights.urihttps://creativecommons.org/licenses/by-nc/4.0/
dc.subjectEngenharia electrotécnica, Engenharia electrotécnica, electrónica e informática
dc.subjectElectrical engineering, Electrical engineering, Electronic engineering, Information engineering
dc.titleDRAFT: An On-line Concurrent Test for Partial and Dynamically Reconfigurable FPGAs
dc.typeArtigo em Livro de Atas de Conferência Internacional
dc.contributor.uportoFaculdade de Engenharia
dc.subject.fosCiências da engenharia e tecnologias::Engenharia electrotécnica, electrónica e informática
dc.subject.fosEngineering and technology::Electrical engineering, Electronic engineering, Information engineering
Appears in Collections:FEUP - Artigo em Livro de Atas de Conferência Internacional

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