Please use this identifier to cite or link to this item:
https://hdl.handle.net/10216/85033| Author(s): | Manuel G. Gericota Gustavo R. Alves José M. Ferreira |
| Title: | The RaT technique for concurrent test of dinamically reconfigurable hardware |
| Issue Date: | 2000 |
| Abstract: | A new class of FPGAs that enable partial and dynamic reconfiguration has been recently introduced into the market, opening exciting possibilities for dynamically reconfigurable hardware systems. While enabling concurrent reconfiguration without disturbing system operation, this technology also raises a new test challenge: the reconfiguration process can activate faults which would otherwise not be visible. This paper proposes a structural concurrent test method that reuses the IEEE 1149.1 infrastructure, exploiting the same dynamic and partially reconfigurable features underlying this test challenge. |
| Subject: | Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática Electrical engineering, Electrical engineering, Electronic engineering, Information engineering |
| Scientific areas: | Ciências da engenharia e tecnologias::Engenharia electrotécnica, electrónica e informática Engineering and technology::Electrical engineering, Electronic engineering, Information engineering |
| URI: | https://hdl.handle.net/10216/85033 |
| Source: | Proceedings of DCIS'00 - XV Design of Circuits and Integrated Systems Conference |
| Document Type: | Artigo em Livro de Atas de Conferência Internacional |
| Rights: | openAccess |
| License: | https://creativecommons.org/licenses/by-nc/4.0/ |
| Appears in Collections: | FEUP - Artigo em Livro de Atas de Conferência Internacional |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| 65723.pdf | The RaT technique for concurrent test of dinamically reconfigurable hardware | 209.96 kB | Adobe PDF |  View/Open |
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