A boundary scan based one channel timing analyser

Abstract

The boundary scan test infrastructure is now widely implemented in the integrated circuit market, especially in the microprocessor and Application-Specific Integrated Circuit arena. While the structural test of printed circuit boards has been considered the driving force behind its broad acceptance, the test community has also addressed the issues of prototype debug and validation. However, the more demanding requirements associated with these issues are not sufficiently covered by the mandatory and optional operating modes described in the IEEE 1149.1 standard, especially for debugging problems associated with real-time operations. Previous work has focused on this problem, having resulted in a new set of user-defined optional instructions addressing the use of the BS register to store in real-time a sequence of contiguous vectors, captured at its parallel inputs without / until / after a certain condition is found. In this paper we describe the trade-off between input channels and storage capacity, by proposing a new operating mode where the BS register is used to capture / store an n-bit sequence captured at one single functional pin, thus acting similarly to a one-channel timing analyser. This non-intrusive operating mode may also be used for field diagnosis and other on-line operations.