Please use this identifier to cite or link to this item:
https://hdl.handle.net/10216/84987Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.other | Miguel L. Silva | |
| dc.creator | Manuel G. Gericota | |
| dc.creator | Gustavo R. Alves | |
| dc.creator | José M. Ferreira | |
| dc.date.accessioned | 2019-02-03T05:43:44Z | - |
| dc.date.available | 2019-02-03T05:43:44Z | - |
| dc.date.issued | 2002 | |
| dc.identifier.other | sigarra:65736 | |
| dc.identifier.uri | https://repositorio-aberto.up.pt/handle/10216/84987 | - |
| dc.description.abstract | Dynamically reconfigurable systems have benefited from a new class of FPGAs recently introduced into the market, which allow partial and dynamic reconfiguration at run time, enabling multiple independent processes from different applications to share the same device, swapping them as needed. When the sequence of tasks to be performed is not predictable, resource allocation decisions have to be made online, producing fragmentation of the FPGA logic space. A rearrangement may be necessary to get enough contiguous space to efficiently implement new incoming processes, avoiding the spreading of their components and, as a result, the degradation of their performance. This paper presents a novel active replication mechanism for configurable logic blocks (CLBs), able to implement online rearrangements, defragmenting the available FPGA resources without disturbing currently running processes. | |
| dc.language.iso | eng | |
| dc.relation.ispartof | Proceedings of the 12th international Conference on Field Programmable Logic andApplications (FPL'02) | |
| dc.rights | openAccess | |
| dc.rights.uri | https://creativecommons.org/licenses/by-nc/4.0/ | |
| dc.subject | Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática | |
| dc.subject | Electrical engineering, Electrical engineering, Electronic engineering, Information engineering | |
| dc.title | On-line defragmentation for run-time partially reconfigurable FPGAs | |
| dc.type | Artigo em Livro de Atas de Conferência Internacional | |
| dc.contributor.uporto | Faculdade de Engenharia | |
| dc.subject.fos | Ciências da engenharia e tecnologias::Engenharia electrotécnica, electrónica e informática | |
| dc.subject.fos | Engineering and technology::Electrical engineering, Electronic engineering, Information engineering | |
| Appears in Collections: | FEUP - Artigo em Livro de Atas de Conferência Internacional | |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| 65736.pdf | On-line defragmentation for run-time partially reconfigurable FPGAs | 1.1 MB | Adobe PDF | ![]() View/Open |
This item is licensed under a Creative Commons License
