Please use this identifier to cite or link to this item: http://hdl.handle.net/10216/84564
Author(s): José Martins Ferreira
Gustavo Alves
J. Ramalho
Manuel Gericota
Title: Board-Level BIST Based on the 1149.1 Standard
Issue Date: 1993
Abstract: The progress in the fields of miniaturisation (surface mount technology, large pin count ICs, etc.) andintegration density (due to feature size reduction, and exploited by the availability of highly sophisticatedCAD design tools) has made it possible to design very complex printed circuit boards (PCBs), whichpresent very high testability requirements. Boundary Scan design and test is now largely accepted as oneof the most promising solutions for this challenge, with an increasing number of off-the-shelf BSTcomponents becoming available, and easy-to-use software tools which automate the development of theboundary scan infrastructure for ASIC design. Board-level test, which was the main driving force behindthe development of the BST standard, is however still waiting for an integrated family of componentsable to address three main requirements: the test of non-BST clusters, analog I/O interface, and board-levelBIST capability. Proposed solutions for these problems have been published and some componentsare available, but a much larger offer for board-level designers is still required.This paper proposes a board-level BIST strategy based on three types of testability building blocks: theinterface to non-BST digital I/O nodes, the interface to analog I/O nodes, and a dedicated test processorproviding the board-level test capability. It is shown that, by following careful design rules, it is possibleto implement all the proposed building blocks in medium-complexity programmable logic devices(PLDs) widely available, therefore providing a low-cost and maximum-flexibility solution for board-levelBIST. Moreover, and since these testability blocks were implemented using a simple and powerfulhardware design language (HDL), any changes due to specific board requirements can easily be made.
Subject: Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática
Electrical engineering, Electrical engineering, Electronic engineering, Information engineering
URI: http://hdl.handle.net/10216/84564
Source: 20ª CAVE (Computer Aided VLSI for Europe) Workshop
Document Type: Artigo em Livro de Atas de Conferência Internacional
Rights: openAccess
License: https://creativecommons.org/licenses/by-nc/4.0/
Appears in Collections:FEUP - Artigo em Livro de Atas de Conferência Internacional

Files in This Item:
File Description SizeFormat 
52338.pdfBoard-Level BIST Based on the 1149.1 Standard389.06 kBAdobe PDFThumbnail
View/Open


This item is licensed under a Creative Commons License Creative Commons