Please use this identifier to cite or link to this item: http://hdl.handle.net/10216/84545
Author(s): Frans de Jong
José S. Matos
José M. Ferreira
Title: Boundary scan test, test methodology, and fault modeling
Issue Date: 1991
Abstract: The test technique called "boundary scan test" (BST) offers new opportunities in testing but confrontsusers with new problems too. The implementation of BST in a chip has become an IEEE standard and users onboard level are the next group to begin thinking about using the new possibilities. This article addresses someof the questions about changes in board-level testing and fault diagnosis. The fault model itself is also affectedby using BST. Trivial items are extended with more sophisticated details in order to complete the fault model.Finally, BST appears to be a test technique that offers a high degree of detectability on board level, but for diagnosis,some additional effort has to be made.
Subject: Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática
Electrical engineering, Electrical engineering, Electronic engineering, Information engineering
Call Number: 52888
URI: http://hdl.handle.net/10216/84545
Document Type: Artigo em Revista Científica Internacional
Rights: openAccess
License: https://creativecommons.org/licenses/by-nc/4.0/
Appears in Collections:FEUP - Artigo em Revista Científica Internacional

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