A framework for fault tolerant real time systems based on reconfigurable FPGAs

Abstract

To increase the amount of logic available to the usersin SRAM-based FPGAs, manufacturers are usingnanometric technologies to boost logic density andreduce costs, making its use more attractive. However,these technological improvements also make FPGAsparticularly vulnerable to configuration memory bit-flipscaused by power fluctuations, strong electromagneticfields and radiation. This issue is particularly sensitivebecause of the increasing amount of configurationmemory cells needed to define their functionality.A short survey of the most recent publications ispresented to support the options assumed during thedefinition of a framework for implementing circuitsimmune to bit-flips induction mechanisms in memorycells, based on a customized redundant infrastructureand on a detection-and-fix controller.