Utilize este identificador para referenciar este registo:
https://hdl.handle.net/10216/84045Registo completo
| Campo DC | Valor | Idioma |
|---|---|---|
| dc.creator | José Martins Ferreira | |
| dc.creator | André V. Fidalgo | |
| dc.creator | Gustavo R. Alves | |
| dc.date.accessioned | 2022-09-08T14:35:00Z | - |
| dc.date.available | 2022-09-08T14:35:00Z | - |
| dc.date.issued | 2006-10 | |
| dc.identifier.other | sigarra:136086 | |
| dc.identifier.uri | https://hdl.handle.net/10216/84045 | - |
| dc.description.abstract | Chip debug infrastructures, present in most recent microprocessors, to execute real time fault injection campaigns. It is based on a debugger customized for fault injection and designed for maximum performance and flexibility. The developed methodology can be applied on the verification of dependable systems. | |
| dc.language.iso | eng | |
| dc.relation.ispartof | 6th European Dependable Computing Conference (EDDC-06) | |
| dc.rights | openAccess | |
| dc.rights.uri | https://creativecommons.org/licenses/by-nc/4.0/ | |
| dc.subject | Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática | |
| dc.subject | Electrical engineering, Electrical engineering, Electronic engineering, Information engineering | |
| dc.title | An enhanced debugger for real-time fault injection | |
| dc.type | Artigo em Livro de Atas de Conferência Internacional | |
| dc.contributor.uporto | Faculdade de Engenharia | |
| dc.subject.fos | Ciências da engenharia e tecnologias::Engenharia electrotécnica, electrónica e informática | |
| dc.subject.fos | Engineering and technology::Electrical engineering, Electronic engineering, Information engineering | |
| Aparece nas coleções: | FEUP - Artigo em Livro de Atas de Conferência Internacional | |
Ficheiros deste registo:
| Ficheiro | Descrição | Tamanho | Formato | |
|---|---|---|---|---|
| 136086.pdf | 40.93 kB | Adobe PDF |  Ver/Abrir |
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