Please use this identifier to cite or link to this item: https://hdl.handle.net/10216/73450
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dc.creatorRui Camacho
dc.date.accessioned2022-09-13T02:28:07Z-
dc.date.available2022-09-13T02:28:07Z-
dc.date.issued2004
dc.identifier.othersigarra:63854
dc.identifier.urihttps://hdl.handle.net/10216/73450-
dc.description.abstractInductive Logic Programming (ILP) has achieved considerable success in a wide range of domains. It is recognized however that eciency is a major obstacle to the use of ILP systems in applications requiring large amounts of data. In this paper we address the problem of eciency in ILP in three steps: i) we survey speedup techniques proposed for sequential execution of ILP systems; ii) we survey dierent ways of parallelizing an ILP system and; ii) adapt and combine the sequential execution speedup techniques in the parallel implementations of an ILP system. We also propose a novel technique to partition the search space into independent sub-spaces that may be adequately searched in parallel.
dc.language.isoeng
dc.relation.ispartofVECPAR 2004 -- High Performance Computing for Computational Science
dc.rightsopenAccess
dc.rights.urihttps://creativecommons.org/licenses/by-nc/4.0/
dc.subjectEngenharia de computadores, Engenharia electrotécnica, electrónica e informática
dc.subjectComputer engineering, Electrical engineering, Electronic engineering, Information engineering
dc.titleFrom sequential to parallel Inductive Logic Programming
dc.typeArtigo em Livro de Atas de Conferência Internacional
dc.contributor.uportoFaculdade de Engenharia
dc.subject.fosCiências da engenharia e tecnologias::Engenharia electrotécnica, electrónica e informática
dc.subject.fosEngineering and technology::Electrical engineering, Electronic engineering, Information engineering
Appears in Collections:FEUP - Artigo em Livro de Atas de Conferência Internacional

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