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Author(s): José Machado da Silva
António Pinho
José Silva Matos
Title: Design for embedded testing of an LNA
Issue Date: 2005
Abstract: In-circuit testing methodologies are required to tackle the evaluation of embedded radio-frequency circuits. This paper presents design considerations for the test circuitry proposed to implement a methodology for on-chip testing a low-noise amplifier. A previously reported test technique consists on applying to the LNA a sequence of stimuli with different amplitudes, and on measuring the output amplitude for each input level. The obtained set of coordinates (Vin, Vout) allows finding the 3rd order polynomial that best fits the LNAs transfer function. The LNA input voltages which lead to the 1dB compression (P1dB) and third-order intercept (IP3) points are then calculated after the polynomial coefficients. The work presented herein addresses the implementation of this method, according the scheme shown in Figure 1, i. e., the design of a variable amplitude oscillator, of the switch to connect it to the LNA input, as well as of the RMS-DC converter to measure the LNAs output power. Their development is based on criteria seeking to minimize power consumption and simplicity. Another design driving aspect addresses the facility of controlling the test operation and of observing the output measures using digital or low frequency signals, making it easier to interface this test scheme with general purpose testers. In spite of the simplicity of the circuits being proposed, good measurement results can be obtained. This concerns namely the RMS-DC converter, which is based on a simple half-wave rectifier. Anyway, simulation results for 1dB compression and third-order intercept points show a good agreement with the expected ones. Alternative, eventually more accurate, RMS-DC converters or received signal strength indicator circuits would provide more accurate results at the cost of a much higher complexity and power consumption. Being a controlled oscillator available at the LNA input, the blocks placed after the LNA along the receiver chain can also be tested in sequence.
Subject: Engenharia electrónica
Electronic engineering
Source: XX Design of Circuits and Integrated Systems
Document Type: Artigo em Livro de Atas de Conferência Internacional
Rights: openAccess
Appears in Collections:FEUP - Artigo em Livro de Atas de Conferência Internacional

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