Please use this identifier to cite or link to this item: https://hdl.handle.net/10216/71522
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dc.creatorFrancisco X. Duarte
dc.creatorJosé Carlos Alves
dc.creatorJosé Machado da Silva
dc.creatorAntónio Pinho
dc.creatorJosé Silva Matos
dc.date.accessioned2019-02-02T16:04:51Z-
dc.date.available2019-02-02T16:04:51Z-
dc.date.issued2005
dc.identifier.othersigarra:69806
dc.identifier.urihttps://repositorio-aberto.up.pt/handle/10216/71522-
dc.description.abstractEmbedded test within integrated systems allows to overcome some of the difficulties found when testing using only an external tester. The reutilization of a reconfigurable FPGA-like block that may exist in certain SoC systems, enables the implementation of on-chip test processors highly optimized to meet the specific requirements of the test procedure for each block. The fast reconfiguration of SRAM-based FPGA blocks allows sharing the same physical area among the set of different circuits that may be necessary to implement the on-chip test suite of the whole system. This paper addresses the high level generation of specific programmable processors for testing different blocks within integrated systems, taking advantage of such existing programmable resources. The work presented herein proposes a methodology and a set of automation tools to enable the automatic generation of dedicated custom processor architectures for specific test operations, as well as the corresponding test programs. This facility can be seen as disposing of a highly flexible and optimised embedded tester, supplied as an intellectual property (IP) module and its software. The approach being proposed is based in the implementation of a test processor as an Application Specific Instruction-Set Processor (ASIP), whose set of conventional and dedicated instructions are automatically derived from a software specification of the test operation to be implemented. The actual configuration of the test processor is determined by the type of instructions the test designer uses in the test program. The processors instruction set is configured automatically from the source code of the program to be run, in order to include only the exact instructions required for that task. The generation of a test processor starts with a software specification of the test operation to be performed. Presently, this specification is done using a program written in an assembly level language whose instruction set comprises all the general purpose instructions supported by the processor core, plus an extra set of complex instructions that are responsible for the operation of the peripheral specific blocks. From this specification, a custom programmable processor is generated as a set of synthesisable HDL modules, including the identification of peripheral blocks associated to specific instructions, and the set of constrains and assignments required to instantiate and map these modules onto the FPGA. These descriptions are then forwarded to the specific FPGA technology mapping and implementation tools, to create an application-specific processor that includes only the instructions referred in the source code.
dc.language.isoeng
dc.relation.ispartofXX Design of Circuits and Integrated Systems
dc.rightsopenAccess
dc.rights.urihttps://creativecommons.org/licenses/by-nc/4.0/
dc.subjectEngenharia electrónica
dc.subjectElectronic engineering
dc.titleA high level test processor and test program generator
dc.typeArtigo em Livro de Atas de Conferência Internacional
dc.contributor.uportoFaculdade de Engenharia
Appears in Collections:FEUP - Artigo em Livro de Atas de Conferência Internacional

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