Please use this identifier to cite or link to this item: http://hdl.handle.net/10216/69954
Author(s): Miguel L. Silva
João Canas Ferreira
Title: Exploiting dynamic reconfiguration of platform FPGAs: implementation issues
Issue Date: 2006
Abstract: The effective use of dynamic reconfiguration requires the designer to address many implementation issues. The market introduction of feature-full platform FPGAs equipped with embedded CPU blocks expands the number of situations where dynamic reconfiguration may be applied to improve overall performance and logic utilization. The paper compares the design of two similar systems supporting dynamic reconfiguration and the issues that were addressed in their implementation. The first system supports 32-bit data transfers between CPU and the dynamically reconfigurable circuits. The other implementation supports 64-bit transfers, but its effective use is more complicated and several restrictions must be taken into account. The work includes a performance comparison of the two designs on several simple tasks, including pattern matching, image processing and hashing. © 2006 IEEE.
Subject: Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática
URI: http://hdl.handle.net/10216/69954
Source: 20th International Parallel and Distributed Processing Symposium, IPDPS 2006
Document Type: Artigo em Livro de Atas de Conferência Internacional
Rights: openAccess
License: https://creativecommons.org/licenses/by-nc/4.0/
Appears in Collections:FEUP - Artigo em Livro de Atas de Conferência Internacional

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