Please use this identifier to cite or link to this item:
https://hdl.handle.net/10216/168269| Author(s): | Gonçalo André Vieira Cardoso |
| Title: | Automated Register Abstraction Layer Generation for UVM-based Verification |
| Issue Date: | 2025-07-18 |
| Subject: | Engenharia electrotécnica, electrónica e informática Electrical engineering, Electronic engineering, Information engineering |
| Scientific areas: | Ciências da engenharia e tecnologias::Engenharia electrotécnica, electrónica e informática Engineering and technology::Electrical engineering, Electronic engineering, Information engineering |
| TID identifier: | 204113547 |
| URI: | https://hdl.handle.net/10216/168269 |
| Document Type: | Dissertação |
| Rights: | embargoedAccess |
| Embargo End Date: | 2030-07-17 |
| Appears in Collections: | FEUP - Dissertação |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| 733049.pdf Restricted Access | Automated Register Abstraction Layer Generation for UVM-based Verification | 3.35 MB | Adobe PDF | View/Open |
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