Automated Register Abstraction Layer Generation for UVM-based Verification

Please use this identifier to cite or link to this item: https://hdl.handle.net/10216/168269

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DC Field	Value	Language
dc.creator	Gonçalo André Vieira Cardoso
dc.date.accessioned	2026-01-26T03:28:11Z	-
dc.date.available	2026-01-26T03:28:11Z	-
dc.date.issued	2025-07-18
dc.date.submitted	2025-07-25
dc.identifier.other	sigarra:733049
dc.identifier.uri	https://hdl.handle.net/10216/168269	-
dc.language.iso	eng
dc.rights	embargoedAccess
dc.subject	Engenharia electrotécnica, electrónica e informática
dc.subject	Electrical engineering, Electronic engineering, Information engineering
dc.title	Automated Register Abstraction Layer Generation for UVM-based Verification
dc.type	Dissertação
dc.date.embargo	2030-07-17
dc.contributor.uporto	Faculdade de Engenharia
dc.identifier.tid	204113547
dc.subject.fos	Ciências da engenharia e tecnologias::Engenharia electrotécnica, electrónica e informática
dc.subject.fos	Engineering and technology::Electrical engineering, Electronic engineering, Information engineering
thesis.degree.discipline	Mestrado em Engenharia Eletrotécnica e de Computadores
thesis.degree.grantor	Faculdade de Engenharia
thesis.degree.grantor	Universidade do Porto
thesis.degree.level	1
rcaap.embargofct	Existência de um acordo entre a FEUP e a empresa, onde ficou acordado um período de confidencialidade de 5 anos e encontra-se explícito o respetivo armazenamento de anexos associados ao documento.
Appears in Collections:	FEUP - Dissertação

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