Fault grading analysis and IP architectural updates to achieve automotive grade standards

Abstract

The objective of this thesis is to study the different methods, tools, architectures that could be applicable to a mixed-signal product in order to increase the stuck@ coverage over the digital circuit part of the respective product, taking into consideration the test time and aiming to minimize the number of test patterns. The automotive industry is migrating from a pure transportation vehicle to more digitally integrated vehicles. The electronic circuit functions are moving from pure basic functions to very complex systems that control not only the vehicle operation but also provide a user interface and can take control of the car to avoid obstacles and perform assisted driving maneuvers. The chips used by automotive OEMs need to meet different standards depending on the function they need to execute. The focus of this thesis will be on ways to improve the fault test coverage of the digital portion of mixed-signals products achieving fault test coverage value >99% for stuck@. The work will focus on the usage of the different fault grading tools as well as analyzing architectures that help to increase the fault test coverage. It would be plus combining with fault grading specific patterns the functional test patterns leading to a reduction on the number of fault grading specific test patterns. The challenge is to achieve the highest coverage numbers without disrupting the analog to digital interface and minimizing the fault grading specific logic. It is upmost to find updates to the current architectures that do not disrupt the current analog development flow, the focus shall be in creating structures in the digital domain that support the coverage improvement. To achieve good results the strategy needs to maximize the usage of the common fault grading structures and a low ration between fault grading structures over functional logical structures (in gate count).