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Author(s): Artur Jorge Alves Antunes
Title: Implementação em Verilog de Codificador/Descodificador Reed-Solomon FEC.
Issue Date: 2017-07-14
Subject: Engenharia electrotécnica, electrónica e informática
Electrical engineering, Electronic engineering, Information engineering
Scientific areas: Ciências da engenharia e tecnologias::Engenharia electrotécnica, electrónica e informática
Engineering and technology::Electrical engineering, Electronic engineering, Information engineering
TID identifier: 201795655
Document Type: Dissertação
Rights: openAccess
Appears in Collections:FEUP - Dissertação

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205906.pdfVerilog Implementation of a Forward Error Correcting Reed Solomon Encoder and Decoder552.67 kBAdobe PDFThumbnail

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