1. Repositório Aberto da Universidade do Porto
  2. FEUP - Faculdade de Engenharia
  3. FEUP - Dissertação
Please use this identifier to cite or link to this item: https://hdl.handle.net/10216/106557
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dc.creatorArtur Jorge Alves Antunes
dc.date.accessioned2025-11-09T13:29:05Z-
dc.date.available2025-11-09T13:29:05Z-
dc.date.issued2017-07-14
dc.date.submitted2017-08-01
dc.identifier.othersigarra:205906
dc.identifier.urihttps://hdl.handle.net/10216/106557-
dc.language.isopor
dc.rightsopenAccess
dc.subjectEngenharia electrotécnica, electrónica e informática
dc.subjectElectrical engineering, Electronic engineering, Information engineering
dc.titleImplementação em Verilog de Codificador/Descodificador Reed-Solomon FEC.
dc.typeDissertação
dc.contributor.uportoFaculdade de Engenharia
dc.identifier.doi10.34626/3y49-td67
dc.identifier.tid201795655
dc.subject.fosCiências da engenharia e tecnologias::Engenharia electrotécnica, electrónica e informática
dc.subject.fosEngineering and technology::Electrical engineering, Electronic engineering, Information engineering
thesis.degree.disciplineMestrado Integrado em Engenharia Electrotécnica e de Computadores
thesis.degree.grantorFaculdade de Engenharia
thesis.degree.grantorUniversidade do Porto
thesis.degree.level1
Appears in Collections:FEUP - Dissertação

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