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3. FEUP - Dissertação

Author(s):	Diogo Alexandre Ribeiro de Sousa
Title:	VLSI design of configurable low-power coarse-grained array architecture
Issue Date:	2017-07-04
Description:	Biomedical signal acquisition from in- or on-body sensors often requires local (on-node) low-level pre-processing before the data are sent to a remote node for aggregation and further processing. Local processing is required for many different operations, which include signal cleanup (noise removal), sensor calibration, event detection and data compression. In this environment, processing is subject to aggressive energy consumption restrictions, while often operating under real-time requirements. These conflicting requirements impose the use of dedicated circuits addressing a very specific task or the use of domain-specific customization to obtain significant gains in power efficiency. However, economic and time-to-market constraints often make the development or use of application-specific platforms very risky. One way to address these challenges is to develop a sensor node with a general-purpose architecture combining a low-power, low-performance general microprocessor or micro-controller with a coarse-grained reconfigurable array (CGRA) acting as an accelerator. A CGRA consists of a fixed number of processing units (e.g., ALUs) whose function and interconnections are determined by some configuration data. The objective of this work is to create an RTL-level description of a low-power CGRA of ALUs and produce a low-power VLSI (standard cell) implementation, that supports power-saving features. The CGRA implementation should use as few resources as possible and fully exploit the intended operation environment. The design will be evaluated with a set of simple signal processing tasks
Subject:	Engenharia electrotécnica, electrónica e informática Electrical engineering, Electronic engineering, Information engineering
Scientific areas:	Ciências da engenharia e tecnologias::Engenharia electrotécnica, electrónica e informática Engineering and technology::Electrical engineering, Electronic engineering, Information engineering
DOI:	10.34626/2wgt-zp06
TID identifier:	201796864
URI:	https://hdl.handle.net/10216/105383
Document Type:	Dissertação
Rights:	openAccess
Appears in Collections:	FEUP - Dissertação

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