VLSI design of configurable low-power coarse-grained array architecture

Diogo Alexandre Ribeiro de Sousa

doi:10.34626/2wgt-zp06

Please use this identifier to cite or link to this item: https://hdl.handle.net/10216/105383

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DC Field	Value	Language
dc.creator	Diogo Alexandre Ribeiro de Sousa
dc.date.accessioned	2025-11-05T03:25:56Z	-
dc.date.available	2025-11-05T03:25:56Z	-
dc.date.issued	2017-07-04
dc.date.submitted	2017-07-14
dc.identifier.other	sigarra:200482
dc.identifier.uri	https://hdl.handle.net/10216/105383	-
dc.description	Biomedical signal acquisition from in- or on-body sensors often requires local (on-node) low-level pre-processing before the data are sent to a remote node for aggregation and further processing. Local processing is required for many different operations, which include signal cleanup (noise removal), sensor calibration, event detection and data compression. In this environment, processing is subject to aggressive energy consumption restrictions, while often operating under real-time requirements. These conflicting requirements impose the use of dedicated circuits addressing a very specific task or the use of domain-specific customization to obtain significant gains in power efficiency. However, economic and time-to-market constraints often make the development or use of application-specific platforms very risky. One way to address these challenges is to develop a sensor node with a general-purpose architecture combining a low-power, low-performance general microprocessor or micro-controller with a coarse-grained reconfigurable array (CGRA) acting as an accelerator. A CGRA consists of a fixed number of processing units (e.g., ALUs) whose function and interconnections are determined by some configuration data. The objective of this work is to create an RTL-level description of a low-power CGRA of ALUs and produce a low-power VLSI (standard cell) implementation, that supports power-saving features. The CGRA implementation should use as few resources as possible and fully exploit the intended operation environment. The design will be evaluated with a set of simple signal processing tasks
dc.language.iso	eng
dc.rights	openAccess
dc.subject	Engenharia electrotécnica, electrónica e informática
dc.subject	Electrical engineering, Electronic engineering, Information engineering
dc.title	VLSI design of configurable low-power coarse-grained array architecture
dc.type	Dissertação
dc.contributor.uporto	Faculdade de Engenharia
dc.identifier.doi	10.34626/2wgt-zp06
dc.identifier.tid	201796864
dc.subject.fos	Ciências da engenharia e tecnologias::Engenharia electrotécnica, electrónica e informática
dc.subject.fos	Engineering and technology::Electrical engineering, Electronic engineering, Information engineering
thesis.degree.discipline	Mestrado Integrado em Engenharia Electrotécnica e de Computadores
thesis.degree.grantor	Faculdade de Engenharia
thesis.degree.grantor	Universidade do Porto
thesis.degree.level	1
Appears in Collections:	FEUP - Dissertação

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