Please use this identifier to cite or link to this item: https://hdl.handle.net/10216/85147
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dc.creatorFilipe Miguel Teixeira Monteiro
dc.date.accessioned2025-11-13T15:20:44Z-
dc.date.available2025-11-13T15:20:44Z-
dc.date.issued2016-07-20
dc.date.submitted2016-07-26
dc.identifier.othersigarra:139550
dc.identifier.urihttps://hdl.handle.net/10216/85147-
dc.descriptionIn this dissertation we propose to develop, implement, and validate a software based clock synchronization algorithm in a many-core processor architecture, specifically the Kalray MPPA-256 architecture. This work was the objective of reducing the effect of clock skew in many-core architectures, so that we can take full advantage of this hardware type in real-time applications.
dc.language.isoeng
dc.rightsopenAccess
dc.rights.urihttps://creativecommons.org/licenses/by-nc/4.0/
dc.subjectEngenharia electrotécnica, electrónica e informática
dc.subjectElectrical engineering, Electronic engineering, Information engineering
dc.titleClock Synchronization for Many-Core Processors
dc.typeDissertação
dc.contributor.uportoFaculdade de Engenharia
dc.identifier.doi10.34626/20ye-sz73
dc.identifier.tid201303272
dc.subject.fosCiências da engenharia e tecnologias::Engenharia electrotécnica, electrónica e informática
dc.subject.fosEngineering and technology::Electrical engineering, Electronic engineering, Information engineering
thesis.degree.disciplineMestrado Integrado em Engenharia Electrotécnica e de Computadores
thesis.degree.grantorFaculdade de Engenharia
thesis.degree.grantorUniversidade do Porto
thesis.degree.level1
Appears in Collections:FEUP - Dissertação

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