1. Repositório Aberto da Universidade do Porto
  2. FEUP - Faculdade de Engenharia
  3. FEUP - Dissertação
Please use this identifier to cite or link to this item: https://hdl.handle.net/10216/68427
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dc.creatorLuís Miguel Granja Gomes
dc.date.accessioned2022-09-13T06:13:33Z-
dc.date.available2022-09-13T06:13:33Z-
dc.date.issued2013-07-17
dc.date.submitted2013-08-09
dc.identifier.othersigarra:26764
dc.identifier.urihttps://hdl.handle.net/10216/68427-
dc.language.isoeng
dc.rightsopenAccess
dc.rights.urihttps://creativecommons.org/licenses/by-nc/4.0/
dc.subjectCiências da engenharia e tecnologias
dc.subjectEngineering and technology
dc.titlePower reduction of a CMOS high-speed interface using Power Gating
dc.typeDissertação
dc.contributor.uportoFaculdade de Engenharia
dc.subject.fosCiências da engenharia e tecnologias
dc.subject.fosEngineering and technology
thesis.degree.disciplineMestrado Integrado em Engenharia Electrotécnica e de Computadores
thesis.degree.grantorFaculdade de Engenharia
thesis.degree.grantorUniversidade do Porto
thesis.degree.level1
Appears in Collections:FEUP - Dissertação

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