Please use this identifier to cite or link to this item:
https://hdl.handle.net/10216/68024| Author(s): | Nelson Tiago Lopes da Silva |
| Title: | Power reduction of a CMOS high speed interface using Clock Gating |
| Issue Date: | 2013-07-17 |
| Subject: | Ciências da engenharia e tecnologias Engineering and technology |
| Scientific areas: | Ciências da engenharia e tecnologias Engineering and technology |
| DOI: | 10.34626/yawa-4a61 |
| URI: | https://hdl.handle.net/10216/68024 |
| Document Type: | Dissertação |
| Rights: | openAccess |
| License: | https://creativecommons.org/licenses/by-nc/4.0/ |
| Appears in Collections: | FEUP - Dissertação |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| 26622.pdf | Power reduction of a CMOS high speed interface using Clock Gating | 2.42 MB | Adobe PDF |  View/Open |
This item is licensed under a Creative Commons License
