Please use this identifier to cite or link to this item:
https://hdl.handle.net/10216/166222| Author(s): | Vinicius Dutra Pirassoli |
| Title: | RISC++: Designing a RISC-V Core via High-Level-Synthesis of C/C++ |
| Issue Date: | 2025-03-20 |
| Subject: | Engenharia electrotécnica, electrónica e informática Electrical engineering, Electronic engineering, Information engineering |
| Scientific areas: | Ciências da engenharia e tecnologias::Engenharia electrotécnica, electrónica e informática Engineering and technology::Electrical engineering, Electronic engineering, Information engineering |
| DOI: | 10.34626/7rt5-7794 |
| TID identifier: | 204120250 |
| URI: | https://hdl.handle.net/10216/166222 |
| Document Type: | Dissertação |
| Rights: | openAccess |
| Appears in Collections: | FEUP - Dissertação |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| 717926.pdf | RISC++: Designing a RISC-V Core via High-Level-Synthesis of C/C++ | 1.21 MB | Adobe PDF |  View/Open |
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