1. Repositório Aberto da Universidade do Porto
  2. FEUP - Faculdade de Engenharia
  3. FEUP - Dissertação
Please use this identifier to cite or link to this item: https://hdl.handle.net/10216/162341
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dc.creatorRenato Pedrosa de Jesus
dc.date.accessioned2026-01-12T08:45:03Z-
dc.date.available2026-01-12T08:45:03Z-
dc.date.issued2024-10-08
dc.date.submitted2024-10-28
dc.identifier.othersigarra:694018
dc.identifier.urihttps://hdl.handle.net/10216/162341-
dc.language.isoeng
dc.rightsopenAccess
dc.subjectEngenharia electrotécnica, electrónica e informática
dc.subjectElectrical engineering, Electronic engineering, Information engineering
dc.titleEvaluating High-Level SystemC Formal Verification Compared to RTL Verification
dc.typeDissertação
dc.contributor.uportoFaculdade de Engenharia
dc.identifier.doi10.34626/4npg-gc66
dc.identifier.tid203861302
dc.subject.fosCiências da engenharia e tecnologias::Engenharia electrotécnica, electrónica e informática
dc.subject.fosEngineering and technology::Electrical engineering, Electronic engineering, Information engineering
thesis.degree.disciplineMestrado em Engenharia Eletrotécnica e de Computadores
thesis.degree.grantorFaculdade de Engenharia
thesis.degree.grantorUniversidade do Porto
thesis.degree.level1
Appears in Collections:FEUP - Dissertação

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