CGRA-RISC: Simulation Infrastructure for Coupling CGRA Accelerator to RISC-V Processor

Abstract

An emergent demand for high-performance and multi-domain computing, such as Deep Learn- ing, has potentiated alternative computing devices, commonly called accelerators. This set of devices includes the Coarse-Grained Reconfigurable Array, a highly parallel and re- configurable architecture. Fundamentally, a CGRA includes Processing Elements subdivided into Functional Units capable of parallel mathematical and logical operations, integrated into a 2D interconnection topology to direct the data transfers between elements. During the design and verification process of a CGRA, a Design Space Exploration (DSE) step is usually required. State-of-the-art design frameworks help throughout this process by automating the generation of configurations or generating the hardware specification. A simulation step typically follows, which reports on the achieved correctness and evaluates different performance metrics. This work will build upon an existing Java-based CGRA simulator, enhance its capabilities, and pair it to a RISC-V simulator that will exchange data and instructions with the accelera- tor, acting as a co-processor. The main objective is to use the integrated simulation platform as a tool for DSE of CGRAs, validation of communication between RISC-V and CGRA, and consequent lowering to actual hardware implementations.