1. Repositório Aberto da Universidade do Porto
  2. FEUP - Faculdade de Engenharia
  3. FEUP - Dissertação
Please use this identifier to cite or link to this item: https://hdl.handle.net/10216/153586
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dc.creatorHélder Tiago da Silva Neves
dc.date.accessioned2025-11-12T16:22:12Z-
dc.date.available2025-11-12T16:22:12Z-
dc.date.issued2023-10-13
dc.date.submitted2023-10-30
dc.identifier.othersigarra:647458
dc.identifier.urihttps://hdl.handle.net/10216/153586-
dc.language.isoeng
dc.rightsembargoedAccess
dc.subjectEngenharia electrotécnica, electrónica e informática
dc.subjectElectrical engineering, Electronic engineering, Information engineering
dc.titleVerilog Modelling and Synthesis of MIPI Multi-Pixel Image Compression
dc.typeDissertação
dc.date.embargo2026-10-12
dc.contributor.uportoFaculdade de Engenharia
dc.identifier.doi10.34626/2ksj-pj13
dc.identifier.tid203423887
dc.subject.fosCiências da engenharia e tecnologias::Engenharia electrotécnica, electrónica e informática
dc.subject.fosEngineering and technology::Electrical engineering, Electronic engineering, Information engineering
thesis.degree.disciplineMestrado em Engenharia Eletrotécnica e de Computadores
thesis.degree.grantorFaculdade de Engenharia
thesis.degree.grantorUniversidade do Porto
thesis.degree.level1
rcaap.embargofctDe acordo com o contrato de confidencialidade assinado por ambas as partes.
Appears in Collections:FEUP - Dissertação

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