Please use this identifier to cite or link to this item:
Author(s): Ciro de Moura Monteiro
Title: RTL Guidelines for Static Power Reduction
Issue Date: 2016-07-12
Description: This work consists on implementing power gating on a sub-system IP, in hopes to reduce static power consumption in chips implemented on low geometry technology. From the results obtained, conclusions are to be made on some lines to guide future low power implementations. This guidelines are to be tested on another component in order to observe their impact on power consumption.
Subject: Engenharia electrotécnica, electrónica e informática
Electrical engineering, Electronic engineering, Information engineering
Scientific areas: Ciências da engenharia e tecnologias::Engenharia electrotécnica, electrónica e informática
Engineering and technology::Electrical engineering, Electronic engineering, Information engineering
TID identifier: 201805766
Document Type: Dissertação
Rights: openAccess
Appears in Collections:FEUP - Dissertação

Files in This Item:
File Description SizeFormat 
244825.pdfRTL Guidelines for Static Power Reduction1.03 MBAdobe PDFThumbnail

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.