Please use this identifier to cite or link to this item: https://hdl.handle.net/10216/105445
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dc.creatorVitor Emanuel Esteves Lopes
dc.date.accessioned2025-11-13T17:19:12Z-
dc.date.available2025-11-13T17:19:12Z-
dc.date.issued2017-07-13
dc.date.submitted2017-07-19
dc.identifier.othersigarra:200864
dc.identifier.urihttps://hdl.handle.net/10216/105445-
dc.descriptionLadder Diagram is a simple graphic language useful to express control in terms of a set of boolean predicates that relate input boolean data to output actuation. Although widely used, LD is not properly designed to express sequential logic. To express sequential logic in a clear and structured way we can use SFC. SFC is a graphical language designed to break sequential control into small tasks and can be easily understood upon quick analysis. Since many industrial processes are sequential by nature and there are still many LD programs in the industry, a tool to extract sequential logic from LD programs and represent it in SFC is needed. From this premise, a software tool is developed in Java programming language. This tool takes a project in PLCopen XML format, extracts the LD program and creates the smaller state-space that represents the obfuscated sequential logic. From this state-space a SFC can be built.
dc.description.abstractLadder Diagram is a simple graphic language useful to express control in terms of a set of boolean predicates that relate input boolean data to output actuation. Although widely used, LD is not properly designed to express sequential logic. To express sequential logic in a clear and structured way we can use SFC. SFC is a graphical language designed to break sequential control into small tasks and can be easily understood upon quick analysis. Since many industrial processes are sequential by nature and there are still many LD programs in the industry, a tool to extract sequential logic from LD programs and represent it in SFC is needed. From this premise, a software tool is developed in Java programming language. This tool takes a project in PLCopen XML format, extracts the LD program and creates the smaller state-space that represents the obfuscated sequential logic. From this state-space a SFC can be built.
dc.language.isoeng
dc.rightsopenAccess
dc.rights.urihttps://creativecommons.org/licenses/by-nc-sa/4.0/
dc.subjectEngenharia electrotécnica, electrónica e informática
dc.subjectElectrical engineering, Electronic engineering, Information engineering
dc.titleConverting LD to SFC (IEC 61131-3)
dc.typeDissertação
dc.contributor.uportoFaculdade de Engenharia
dc.identifier.doi10.34626/mdm0-re76
dc.identifier.tid201804026
dc.subject.fosCiências da engenharia e tecnologias::Engenharia electrotécnica, electrónica e informática
dc.subject.fosEngineering and technology::Electrical engineering, Electronic engineering, Information engineering
thesis.degree.disciplineMestrado Integrado em Engenharia Electrotécnica e de Computadores
thesis.degree.grantorFaculdade de Engenharia
thesis.degree.grantorUniversidade do Porto
thesis.degree.level1
Appears in Collections:FEUP - Dissertação

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