Please use this identifier to cite or link to this item: https://hdl.handle.net/10216/84044
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dc.creatorJosé Martins Ferreira
dc.creatorAndré V. Fidalgo
dc.creatorGustavo R. Alves
dc.date.accessioned2022-09-12T03:16:11Z-
dc.date.available2022-09-12T03:16:11Z-
dc.date.issued2006-06
dc.identifier.othersigarra:136091
dc.identifier.urihttps://hdl.handle.net/10216/84044-
dc.description.abstractThis paper presents a set of modifications to common processor on-chip debugging infrastructures to support the execution of fault injection campaigns. The proposed solution is applicable to different target architectures and imposes a very low logic overhead, providing a flexible and efficient mechanism for verifying and validating fault tolerant components.
dc.language.isoeng
dc.rightsopenAccess
dc.rights.urihttps://creativecommons.org/licenses/by-nc/4.0/
dc.subjectEngenharia electrotécnica, Engenharia electrotécnica, electrónica e informática
dc.subjectElectrical engineering, Electrical engineering, Electronic engineering, Information engineering
dc.titleOCD-FI: On-Chip Debug and Fault Injection
dc.typePoster em Conferência Internacional
dc.contributor.uportoFaculdade de Engenharia
dc.subject.fosCiências da engenharia e tecnologias::Engenharia electrotécnica, electrónica e informática
dc.subject.fosEngineering and technology::Electrical engineering, Electronic engineering, Information engineering
Appears in Collections:FEUP - Poster em Conferência Internacional

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