Please use this identifier to cite or link to this item:
https://hdl.handle.net/10216/69951
Author(s): | Miguel L. Silva João Canas Ferreira José Silva Matos |
Title: | Flexible use of IP gores on dynamically reconfigurable systems |
Issue Date: | 2008 |
Abstract: | The advantages of dynamic reconfiguration can only be exploited if devices, tools and design flows are available to support the partial reconfiguration of FPGA-based systems. For a number of applications, enabling the swap of cores at run-time, under software control, is an essential feature that allows tailoring the system response to the needs of different methods, standards and power/performance requirements. The paper proposes a method to support the exchange of intellectual property (IP) cores during system operation. The approach is based on the definition of a base system, with reserved or dynamic areas, where different cores may be plugged in, providing timesharing of the system resources. It is shown how bitstream-level IP cores can be used in a design flow that allows different cores to be used in one or more host areas, with minimal intervention from the designer. A demonstration system along with example applications are presented to illustrate the approach. |
Subject: | Engenharia electrotécnica, electrónica e informática Electrical engineering, Electronic engineering, Information engineering |
Scientific areas: | Ciências da engenharia e tecnologias::Engenharia electrotécnica, electrónica e informática Engineering and technology::Electrical engineering, Electronic engineering, Information engineering |
URI: | https://hdl.handle.net/10216/69951 |
Source: | Proceedings of the XXIII Conference on Design of Circuits and Integrated Systems |
Document Type: | Artigo em Livro de Atas de Conferência Internacional |
Rights: | openAccess |
License: | https://creativecommons.org/licenses/by-nc/4.0/ |
Appears in Collections: | FEUP - Artigo em Livro de Atas de Conferência Internacional |
This item is licensed under a Creative Commons License