CMOS Phase Modulator for Polar Transmitters

Abstract

Wireless communications are developing quickly. The search for higher data rates is pushing the integration of wideband code-division multiple access (WCDMA) into Global System for Mobile Communications (GSM) and Enhanced Data Rates for GSM Evolution (EDGE) networks. A critical part of the wireless device is the radio transceiver which consists of a receiver and a transmitter. Wireless receivers typically depend on low-intermediate frequency (IF) and direct conversion architectures that convert the received signal directly to baseband frequencies. Wireless transmitters usually employ one of two popular architectures, direct up conversion or polar modulation.It is important to develop a transmitter with a high efficiency and linearity, and with a low system complexity. So, one of the greatest solution is the use of a polar transmitter. A polar transmitter is mainly constituted by two blocks which one is responsible for the phase modulator and the other one for the amplitude modulator. The aim of this dissertation is building a phase modulator for a polar transmitter. This modulator cannot be fully digitally because those architectures have a great power consumption due to the use of multiplexers with a significative number of inputs. Based on this, we decided to follow a mixed signal approach. This modulator is composed by three main blocks: a phase interpolator, a phase signal divider and a sign bit. The crucial cell of this project is the phase interpolator, which is responsible for performing the final RF phase modulation. It receives two digital differential orthogonal signals, thus those signals define which quadrant of unit-circle will be performed. Also, it receives a baseband signal which will select the output phase in the desired quadrant. To select the desired quadrant to perform it was developed a sign bit cell which is responsible for select the input signals of the interpolator. To obtain those four input RF signals it was used a frequency signal divider composed by latches which receive a signal with a frequency two times greater than the required. A high performance phase modulator must have a low phase noise , which implies an increase of power consumption. Based on this, the goal of this project was achieved a great phase resolution with a better power consumption without damaging the output phase per quadrant.In this project, it was achieved a 5-bit resolution, per quadrant, for 360uW power consumption.