Automatic implementation of a re-configurable logic over ASIC design flow

Abstract

The available density and complexity on Integrated Circuits (IC) has been increasing, following the improvement of technologies to design and fabric ICs leading to a challenging evolution, in the complexity of digital ICs on SoC design, to the semiconductor industry. As so extensive validation prior to fabrication as become increasingly demanding to ensure design correctness of the produced circuit.At the same time, with the current demand for faster turnaround development cycles, major interoperability tests are already performed in actual silicon, as errors can result on testing , the disposal of the produced chip and the need to create a new production cycle results in time and resources wasting. One of the clear solutions to this problem is the replacement of the original fixed logic with a reprogrammable one.This type of architecture can empower the designer the ability to perform minor updates, on site, changing minor errors and adding some needed, minor, functionalities.The main objective of the thesis, is to study and develop a generic configurable hardware structure, and create a new design flow that can be integrated into the normal work of the IC developer, that can be used in multiple projects and technologies, to create an adaptable architecture suitable to different implementations.